Microcontroller Programming

Transcript

Universität Dortmund
Embedded Systems
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Embedded
“specialized processor targeted for a specific application”
Microcontroller Programming
Embedded Media Processing
Systems concern:
Metodologie di Progettazione Hardware-Software
- Application involving a large
number of data blocks (image,
video, audio, speech, … , also
combination of this)
- Signal processing
- Real time nature
Eng. Marco Benocci
[email protected]
- Portability (battery life
consideration)
Photo: http://www.geekzone.co.nz
- 1-
Eng. Marco Benocci – Microcontroller Programming – MPHS 2008/2009
- 2-
Digital Processor
IEEE 1451
IEEE 1451.0 – This portion of the standard defines the structure of the TEDS
(Transducer Electronic Data Sheets) the interface between .1 and .X, message
exchange protocols and the command set for the transducers.
• Microprocessor
ALU+ sequencer + register (no memory or peripherals)
IEEE 1451.1 – Specifies collecting and distributing information over a conventional IP
network.
• Microcontroller
IEEE 1451.2 – Wired transducer interface – 12 wire bus working on a revision which
will put IEEE 1451 on RS-232, RS-485 and USB.
Processor + data/program memory
IEEE 1451.3 – This is the information to make multi-drop IEEE 1451 sensors work
within a network.
• Digital Signal Processor (DSP)
Microprocessor
processing
with
optimized
architecture
IEEE 1451.4 – This portion of the standard specifies the requirements for TEDS
for
(Transducer Electronic Data Sheets). This is software only.
signal
IEEE 1451.5 – This section of the standard specifies information that will enable 1451
compliant sensors and devices to communicate wirelessly, eliminating the monetary
and time costs of installing cables to acquisition points. The IEEE is currently working
on three different standards, 802.11, Bluetooth and ZigBee.
• Digital Signal Controller (DSC)
IEEE 1451.6 – This is the information required for the CAN (consolidated auto
DSP + memory + peripheral interfaces
network) bus.
- 3-
- 4-
Serial Interface 1/3
UART Universal Asynchronous Receiver/Tramsmitter
TA, TB: Programmable Timers A, B
RTC: Real Time Clock
IC Inter Communication Bus
GPIO: General Purpose Input Output
WD: Watchdog Timer
SPI Serial Peripheral Interface
HI: Host Interface
- 5-
- 6-
Wireless Embedded solution
CAN: Controller Area Network
used in cars and other equipment;
TTP: Time-Triggered-Protocol
•
CNI: Communication Network Interface: interface between communication
controller and the host computer within a node of a distributed system
•
Composability: various components of a software system can be developed
independently and integrated at a late stage development
•
Fail Silence: A subsystem is fail-silent if it either produces correct results or no
results at all
•
FTU: Fault-Tolerance Unit
•
SRU: Smallest Replaceable Unit
differential signaling with twisted pairs,
arbitration using CSMA/CA,
throughput between 10kbit/s and 1 Mbit/s,
low and high-priority signals,
maximum latency of 134 µs for high priority signals,
coding similar to RS-232
Profibus: Process Field Bus
Designed for factory and process automation.
Focus on safety
FlexRay
•
Improved error tolerance and time-determinism
•
Meets requirements with transfer rates >> CAN std.
•
High data rate can be achieved:
–
initially targeted for ~ 10Mbit/sec;
–
design allows much higher data rates
•
TDMA: fixed time slot with exclusive access to the bus
•
Cycle subdivided into a static and a dynamic segment.
•
Exclusive bus access enabled for short time in each case.
Claiming 20% market share for field busses.
Speed:
•
•
•
≦ 93.75 kbit/s (1200 m)
1500 kbits/s (200m)
12 Mbit/s (100m)
Integration with Ethernet via Profinet.
•
Dynamic segment for transmission of variable length information.
•
Fixed priorities in dynamic segment; transmissions starts at end of slot of lower
priority bus node. Bandwidth used when it is actually needed.
- 7-
- 8-
ARM on the market
Real Time operating system
Mcbstr912
ARM:
- low power consumption
- fast execution for watt
- good backward compatility
- cheap
- large kind of core
- MARKETING
Marvell XSCALE
PXA310
ARM1176JZF
• scheduling
• event-driven execution model (fine-grained power management )
• component library (network protocols, distributed services, sensor
drivers, and data acquisition)
• minimizing code size
• enables rapid innovation and implementation
Applications
• physiological monitoring for diagnosing, treating, tracking, and studying
diseases and disorders
• biokinetic monitoring for improving physical medicine and rehabilitation
• human-computer interactions; and education and entertainment through
interactive games
"you-see-linux"
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- 10 -
ASM-C-JAVA(?)
Why use assembly?
PROS:
• can be finely tuned
• most performance (time-critical operations)
• smaller code space
Java is ready?
Ada - U.S. DoD. Popular in the avionics and military world
BASIC - One place it's popular is in the Parallax BASIC Stamp
family of microcontrollers
C - AT&T Bell Labs
CONS:
• hard to maintain
• no portability to other processors
C++ - AT&T Bell Labs
FORTH - Charles Moore. Originally designed for real-time control
of telescopes. Small, but fiercely loyal user-base
C? ☺
• high-level language
• interfaces easily to assembly language (inline)
• efficiency (speed/space)
• easier sw development
• standard C libraries
• portability (ISO/IEC 9899:1999 C)
Common Embedded
High Level Languages
Java - Sun. Becoming more popular
- 11 -
- 12 -
Smart sensor
Tmote Sky Platform
• intelligence capabilities (self-diagnostics, self-identification, selfadaptation, decision-making)
• functions built-in microcontroller (ASIC) or application-specific
instruction processor (ASIP) or DSP to modify its performance
• the measuring process can be optimized for maximum accuracy,
speed and power consumption.
• features:
• adaptability
• accuracy
• reliability
http://www.moteiv.com
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14
- 14 -
MSP430 architecture
Memory Map & Organization
• von-Neumann architecture
• one address space shared with special
function registers (SFRs), peripherals,
RAM, and Flash/ROM memory
• Flash and RAM can be used for both
code and data
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Internal Register
Data Representation
Program Counter (PC)
2-complement
Points to the next instruction to be executed
Stack Pointer (SP)
Store the return addresses of subroutine calls and
interrupts
Status Register (SR)
Source or destination register
!
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- 18 -
Instruction Set
Addressing Modes
• 27 core instructions and 24 emulated instructions
• 3 core-instruction formats: (i) Dual-operand, (ii) Singleoperand, (iii) Jump
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- 20 -
Machine Cycles for
Format I Instructions
Machine Cycles for
Format II/III Instructions
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- 22 -
DIRECTIVES
The Assembler supports a number of directives. The directives are
not translated directly into opcodes. Instead, they are used to adjust
the location of the program in memory, define macros, ...
Directive
Description
DEF
Define a symbolic name on a register
EQU
Set a symbol equal to an expression
INCLUDE
Read source from another file
MACROS
Macros are very useful for doing something that is done often but for
which a procedure can’t be use.
Macros are substituted when the program is compiled to the code
which they contain.
Example
- 23 -
- 24 -
SUBROUTINES 1/2
SUBROUTINES 2/2
Not like macro, subroutine did not save program storage space.
Only stored once in the code.
To ensure continued execution of the sequence following the subroutine
call you need to return to the caller.
Subroutines always start with a label
i.e.. delay of 10 cycles
Name op
#Clocks
rcall
3
Nop
1
ret
4
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- 26 -
Operating Modes
Principles for Low-Power Applications
• System clock to maximize the time in LPM3 (LPM3 power consumption
is less than 2 µA typical with both a real-time clock function and all interrupts active)
• 32-kHz watch crystal for ACLK; CPU clocked from the DCO
• Interrupts to wake the processor and control program flow
• Peripherals should be switched on only when needed
• Use low-power integrated peripheral modules in place of software
driven functions. (i.e. example Timer_A and Timer_B can automatically generate PWM
and capture external timing, with no CPU resources)
• Branching and fast table look-ups in place of flag polling and long
software calculations
• Avoid frequent subroutine and function calls due to overhead
• For longer software routines, single-cycle CPU registers should be
used.
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- 28 -
System Reset / Initialization
C Examples - Operating Modes
C – programming msp430x14x.h
/************************
* STATUS REGISTER BITS
************************/
…
#include "In430.h“
#define C
0x0001
#define Z
0x0002
#define N
0x0004
#define V
0x0100
#define GIE 0x0008
#define CPUOFF 0x0010
#define OSCOFF 0x0020
#define SCG0 0x0040
#define SCG1 0x0080
/* Low Power Modes coded with
Bits 4-7 in SR */
/* Begin #defines for assembler */
#ifndef __IAR_SYSTEMS_ICC
#define LPM0 CPUOFF
#define LPM1 SCG0+CPUOFF
#define LPM2 SCG1+CPUOFF
#define LPM3 SCG1+SCG0+CPUOFF
#define LPM4 SCG1+SCG0+OSCOFF+CPUOFF
/* End #defines for assembler */
#else /* Begin #defines for C */
#define LPM0_bits CPUOFF
#define LPM1_bits SCG0+CPUOFF
#define LPM2_bits SCG1+CPUOFF
#define LPM3_bits SCG1+SCG0+CPUOFF
#define LPM4_bits SCG1+SCG0+OSCOFF+CPUOFF
#define LPM0
_BIS_SR(LPM0_bits) /* Enter LP Mode 0 */
#define LPM0_EXIT _BIC_SR(LPM0_bits) /* Exit LP Mode 0 */
#define LPM1
#define LPM2
#define LPM3
#define LPM4
#endif /* End #defines for C */
/* - in430.h Intrinsic functions for the MSP430
*/
unsigned short _BIS_SR(unsigned short);
unsigned short _BIC_SR(unsigned short);
- 29 -
Init Cond After System Reset
Software Initialization
After a POR, the initial MSP430
conditions are:
After a system reset initialize for
application requirements:
• RST/NMI pin in the reset mode
• I/O pins in input mode
• peripheral modules/registers as
default
• Status register (SR) is reset.
• watchdog timer powers up in wd
mode
• Program counter (PC) loaded with
address contained at reset vector
location (0FFFEh). CPU execution
begins at that address.
• Initialize the SP to top of the
RAM
• Initialize watchdog
• Configure peripheral modules
- 30 -
Basic Clock System
Interrupts
• One DCO, internal digitally
controlled oscillator
• 3 types
System reset
(Non)-maskable
NMI
Maskable
Generated on-chip RC-type
frequency controlled by SW + HW
• One LF/XT oscillator
LF: 32768Hz
XT: 450kHz .... 8MHz
• Interrupt
priorities are
fixed and defined
by the
arrangement of
modules
• Second LF/XT2 oscillator
Optional XT: 450kHz .... 8MHz
• Clocks:
ACLK auxiliary clock ACLK
MCLK main system clock MCLK
SMCLK sub main system clock
- 31 -
- 32 -
(Non)-Maskable Interrupts (NMI)
NMI Interrupt Handler
• Sources
An edge on the RST/NMI pin when configured in
NMI mode
An oscillator fault occurs
An access violation to the flash memory
• Are not masked by GIE (General Interrupt
Enable), but are enabled by individual
interrupt enable bits (NMIIE, OFIE,
ACCVIE)
- 33 -
- 34 -
Maskable Interrupts
Interrupt acceptance
1) Any currently executing instruction is completed.
2) The PC, which points to the next instruction, is pushed onto
the stack.
3) The SR is pushed onto the stack.
4) The interrupt with the highest priority is selected if multiple
interrupts occurred during the last instruction and are pending
for service.
5) The interrupt request flag resets automatically on single-source
flags. Multiple source flags remain set for servicing by
software.
6) The SR is cleared with the exception of SCG0, which is left
unchanged. This terminates any low-power mode. Because
the GIE bit is cleared, further interrupts are disabled.
7) The content of the interrupt vector is loaded into the PC: the
program continues with the interrupt service routine at that
Takes 6 cc to execute
address.
• Caused by peripherals with interrupt
capability
• Each can be disabled individually by
an interrupt enable bit
• All can be disabled by GIE bit in the status
register
- 35 -
- 36 -
Return from Interrupt
Interrupt Vectors
RETI - Return from Interrupt Service Routine
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
1) The SR with all previous settings pops from the stack. All
previous settings of GIE, CPUOFF, etc. are now in effect,
regardless of the settings used during the interrupt service
routine.
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
2) The PC pops from the stack and begins execution at the
point where it was interrupted.
Takes 5 cc to execute
- 37 -
PORT2_VECTOR
UART1TX_VECTOR
UART1RX_VECTOR
PORT1_VECTOR
TIMERA1_VECTOR
TIMERA0_VECTOR
ADC_VECTOR
UART0TX_VECTOR
UART0RX_VECTOR
WDT_VECTOR
COMPARATORA_VECTOR
TIMERB1_VECTOR
TIMERB0_VECTOR
NMI_VECTOR
RESET_VECTOR
1 * 2
2 * 2
3 * 2
4 * 2
5 * 2
6 * 2
7 * 2
8 * 2
9 * 2
10 * 2
11 * 2
12 * 2
13 * 2
14 * 2
15 * 2
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
0xFFE2
0xFFE4
0xFFE6
0xFFE8
0xFFEA
0xFFEC
0xFFEE
0xFFF0
0xFFF2
0xFFF4
0xFFF6
0xFFF8
0xFFFA
0xFFFC
0xFFFE
Port 2 */
UART 1 Transmit */
UART 1 Receive */
Port 1 */
Timer A CC1-2, TA */
Timer A CC0 */
ADC */
UART 0 Transmit */
UART 0 Receive */
Watchdog Timer */
Comparator A */
Timer B 1-7 */
Timer B 0 */
Non-maskable */
Reset [Highest Pr.] */
- 38 -
Interrupt Service Routines
Basic Clock System
•
Interrupt Service Routine declaration
DIVA
// Func. declaration
Interrupt[int_vector] void myISR (Void);
2
LFXTCLK
/1, /2, /4, /8
OscOff
Interrupt[int_vector] void myISR (Void)
{
// ISR code
}
XTS
ACLKGEN
SELM DIVM CPUOff
High frequency
XT oscillator, XTS=1
EXAMPLE
Vcc
Vcc
Rsel SCG0
2
DCO
MOD
3
0
Interrupt[TIMERA0_VECTOR] void myISR (Void)
{
// ISR code
}
P2.5
/Rosc
2
1
DCOR
DCGenerator
DCGEN
2
3
0,1
Low power
LF oscillator, XTS=0
Interrupt[TIMERA0_VECTOR] void myISR (Void);
ACLK
Auxiliary Clock
5
SELS
DCOCLK
MCLK
MCLKGEN
Main System Clock
DIVS SCG1
2
Digital Controlled Oscillator DCO
0
Modulator MOD
1
SMCLK
/1, /2, /4, /8, off
+
DCOMOD
/1, /2, /4, /8, off
SMCLKGEN
Sub-System Clock
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.
The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).
- 39 -
- 40 -
Watchdog Timer
C Example - Basic Clock Module
WDT operating modes:
How to select the Crystal Clock
void selectclock(void)
{
IFG2=0;
/* reset interrupt flag register 1 */
IFG1=0;
/* reset interrupt flag register 2 */
BCSCTL1|=XTS;
/*attach HF crystal (4MHz) to XIN/XOUT
do {
/*wait in loop until crystal is stable*/
IFG1&=~OFIFG;
}while(OFIFG&IFG1);
Delay();
IFG1&=~OFIFG;
• performs a controlled-system restart after a software problem
occurs. If the selected time interval expires, a system reset is
generated.
*/
• interval timer, to generate an interrupt after the selected time interval.
WDTCTL
0120h
MDB, HighByte
MDB, LowByte
R/W
7
/*Reset osc. fault flag again*/
Password Compare
}
How to select a clock for MCLK
Read:HighByte is 069h
EQU
Write: HighByte is 05Ah, otherwise
security key is violated
HOLD
0
NMIES
NMI
TMSEL
CNTCL
SSEL
IS1
ISO
WDT 16-bit Control Register with Write Protection
BCSCTL2=SELM0+SELM1;
/*Then set MCLK same as LFXT1CLK*/
TACTL=TASSEL0+TACLR+ID1;
/*USE ACLK/4 AS TIMER_A INPUT CLOCK
(1MHz) */
- 41 -
- 42 -
Watchdog Timer
C Example - Watchdog Timer
How to select timer mode
/* WDT is clocked by fACLK (assumed 32Khz) */
WDTCL=WDT_ADLY_250; // WDT 250MS/4 INTERVAL TIMER
IE1 |=WDTIE;
// ENABLE WDT INTERRUPT
How to stop watchdog timer
WDTCTL=WDTPW + WDTHOLD ;
// stop watchdog timer
Assembly programming
WDT_key
.equ
05A00h
; Key to access WDT
WDTStop mov
#(WDT_Key+80h),&WDTCTL ; Hold Watchdog
WDT250
mov
#(WDT_Key+1Dh),&WDTCTL ; WDT, 250ms Interval
- 43 -
- 44 -
Digital I/O
C Examples - WDT
//***************************************************************
******
// MSP-FET430P140 Demo - WDT Toggle P1.0, Interval ISR, 32kHz
ACLK
//
// Description; Toggle P1.0 using software timed by WDT ISR.
// Toggle rate is exactly 250ms based on 32kHz ACLK WDT clock
source.
// In this example the WDT is configured to divide 32768 watchcrystal(2^15)
// by 2^13 with an ISR triggered @ 4Hz.
// ACLK= LFXT1= 32768, MCLK= SMCLK= DCO~ 800kHz
// //*External watch crystal installed on XIN XOUT is required
for ACLK*
//
//
//
MSP430F149
//
----------------//
/|\|
XIN|//
| |
| 32kHz
//
--|RST
XOUT|//
|
|
//
|
P1.0|-->LED
//
// M.Buccini
// Texas Instruments, Inc
// August 2003
// Built with IAR Embedded Workbench Version: 1.26B
// December 2003
// Updated for IAR Embedded Workbench Version: 2.21B
//**********************************************************
Port1 Port3
…
Port2 Port6
#include <msp430x14x.h>
void main(void)
{
// WDT 250ms, ACLK, interval timer
WDTCTL = WDT_ADLY_250;
IE1 |= WDTIE; // Enable WDT
interrupt
P1DIR |= 0x01; // Set P1.0 to
output direction
// Enter LPM3 w/interrupt
_BIS_SR(LPM3_bits + GIE);
}
yes
yes
no
Interrupt Enable Register PxIE
yes
no
Interrupt Flag Register PxIFG
yes
no
Direction Register PxDIR
yes
yes
Output Register PxOUT
yes
yes
yes
yes
P1.
P2.
7
P3.
6
5
4
3
2
1
0
P4.
• Up to 6 digital I/O ports implemented: P1-P6
• Ports P1 and P2 have interrupt capability (rising
/falling edge) - Only transitions, not static levels,
cause interrupts
P5.
P6.
- 45 -
yes
Input Register PxIN
// Watchdog Timer interrupt service
routine
interrupt[WDT_TIMER] void
watchdog_timer(void)
{
P1OUT ^= 0x01;
// Toggle P1.0
using exclusive-OR
}
Function Select Register PxSEL
Interrupt Edge Select Register PxIES
- 46 -
Digital I/O Registers Operation
Timer_A 16-bit Counter
•
PnIN: Input Register. Pull up/down value:
• Bit = 0: The input is low (pull down)
• Bit = 1: The input is high (pull up)
•
PnOUT: Output Registers. Value to be output:
• Bit = 0: The output is low
• Bit = 1: The output is high
•
15
PnDIR: Direction Registers.
•
0
TACTL
Input
Select
unused
• Bit = 0: The port pin is switched to input direction
• Bit = 1: The port pin is switched to output direction
160h
rw(0)
PnSEL: Function Select Registers.
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Input
Divider
rw(0)
Mode
Control
rw(0)
• Bit = 0: I/O Function is selected for the pin
• Bit = 1: Peripheral module function is selected for the pin
•
P1IFG, P2IFG: Interrupt Flag
• Bit = 0: No interrupt is pending
• Bit = 1: An interrupt is pending
•
SSEL1 SSEL0
0
0
0
1
1
0
1
1
P1IES, P2IES: Interrupt Edge Select Registers
• Bit = 0: The PnIFGx flag is set with a low-to-high transition
• Bit = 1: The PnIFGx flag is set with a high-to-low transition
- 47 -
ID1
ID0
0
0
1
1
0
1
0
1
unTAIE TAIFG
used CLR
rw(0)
rw(0)
MC1
MC0
0
0
1
1
0
1
0
1
rw(0)
(w)(0)
rw(0)
rw(0)
Stop Mode
Up Mode
Continuous Mode
Up/Down Mode
1/1, Pass
1/2
1/4
1/8
TACLK
ACLK
MCLK
INCLK
- 48 -
Timer_A - Capture Compare Blocks
Timer_A - Counting Modes
Overflow x
COVx
Logic
Capture Path
Timer Bus
Data Bus
Stop/Halt Mode
CMPx
CCISx1 CCISx0
0
1
2
3
UP/DOWN Mode
Timer is halted with the next +CLK
Timer counts between 0 and CCR0 and 0
0FFFFh
CCIxA
CCIxB
GND
VCC
CCMx1
0
0
1
1
15
1
Capture
Mode
Timer
Clock
0
Synchronize
Capture
CCMx0
0 Disabled
1 Pos. Edge
0 Neg. Edge
1 Both Edges
CCR0
Capture/Compare Register
CCRx
Capture
UP/DOWN Mode
0
SCSx
15
0
Comparator
to Port0x
0h
EQUx 0
CAPx
1
Compare Path
EN
A
CCIx
UP Mode
Set_CCIFGx
Y
SCCIx
Continuous Mode
Timer counts between 0 and CCR0
Timer continuously counts up
0FFFFh
Continuous Mode
CCRx
0172h
to
017Eh
15
2
15
rw(0)
15
CCTLx
162h
to
16Eh
2
rw(0)
rw(0)
CAPTURE
MODE
rw(0)
0FFFFh
0
INPUT
SELECT
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
SCS
SCCI
unused
rw(0)
rw(0)
rw(0)
rw(0)
CAP
rw(0)
rw(0)
rw(0)
rw(0)
OUTMODx
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
CCIE CCI
OUT COV CCIFG
rw(0)
rw(0)
r
rw(0)
CCR0
0
rw(0)
0
0h
0h
rw(0)
- 49 -
- 50 -
Timer_A - Output Units 2/2
Timer_A - Output Units 1/2
Timer Clock
TAx
EQUx
Output
EQU0
UP Mode
OUTx (CCTLx.2)
Logic
D
Set
Timer counts between 0 and CCR0
Output Signal Outx
Q
To Output Logic TAx
Timer Clock
Reset
POR
Output Mode 0
OUTx
OMx2 OMx1 OMx0
OMx2 OMx1 OMx0 Function
Operational Conditions
0
0
0
Output Mode
Outx signal is set according to Outx bit
0
0
1
Set
EQUx sets Outx signal clock synchronous with timer clock
0
1
0
PWM Toggle/Reset
EQUx toggles Outx signal, reset with EQU0, clock sync. with timer clock
0
1
1
PWM Set/Reset
EQUx sets Outx signal, reset with EQU0, clock synchronous with timer clock
1
0
0
Toggle
EQUx toggles Outx signal, clock synchronous with timer clock
1
0
1
Reset
EQUx resets Outx signal clock synchronous with timer clock
1
1
0
PWM Toggle/Reset
EQUx toggles Outx signal, set with EQU0, clock synchronous with timer clock
1
1
1
PWM Set/Reset
EQUx resets Outx signal, set with EQU0, clock synchronous with timer clock
- 51 -
- 52 -
Comparator_A
C Examples - CCR0 Contmode ISR, TA_0 ISR
Comparator_A is an analog
voltage comparator
//***************************************************************
// MSP-FET430P140 Demo - Timer_A Toggle P1.0,
// CCR0 Contmode ISR, DCO SMCLK
// Description; Toggle P1.0 using software and TA_0 ISR. Toggle
rate is
// set at 50000 DCO/SMCLK cycles. Default DCO frequency used for
TACLK.
// Durring the TA_0 ISR P0.1 is toggled and 50000 clock cycles are
added to
// CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is
normally off and
// used only durring TA_ISR.
// ACLK = n/a, MCLK = SMCLK = TACLK = DCO~ 800k
//
//
//
MSP430F149
//
--------------//
/|\|
XIN|//
| |
|
//
--|RST
XOUT|//
|
|
//
|
P1.0|-->LED
//
// M. Buccini
// September 2003
// December 2003
//*****************************************************************
*****
• Supports precision slope
analog-to-digital
conversions
• Supply voltage
supervision, and
• Monitoring of external
analog signals.
- 53 -
#include <msp430x14x.h>
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
// Stop WDT
P1DIR |= 0x01;
// P1.0 output
CCTL0 = CCIE;
// CCR0 interrupt enabled
CCR0 = 50000;
TACTL = TASSEL_2 + MC_2; // SMCLK, contmode
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
// Timer A0 interrupt service routine
interrupt[TIMERA0_VECTOR] void TimerA(void)
{
P1OUT ^= 0x01; // Toggle P1.0
CCR0 += 50000; // Add Offset to CCR0
}
- 54 -
C Example - UART 9600
USART: UART/SPI
//*******************************************************************
***********
// MSP-FET430P140 Demo - USART1, Ultra-Low Pwr UART 9600 Echo ISR,
32kHz ACLK
//
// Description: Echo a received character, RX ISR used. Normal mode
is LPM3,
// USART1 RX interrupt triggers TX Echo.
// ACLK = UCLK1 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k
// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41
(0003h 4Ah )
// //* An external watch crystal is required on XIN XOUT for ACLK
*//
//
//
//
MSP430F149
//
----------------//
/|\|
XIN|//
| |
| 32kHz
//
--|RST
XOUT|//
|
|
//
|
P3.6|----------->
//
|
| 9600 - 8N1
//
|
P3.7|<----------//
// //
// M. Buccini
// October 2003
// January 2004
//*******************************************************************
***********
- 55 -
#include
<msp430x14x.h>
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
// Stop WDT
P3SEL |= 0xC0;
//3.6,7 = USART1 TXD/RXD
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
UCTL1 |= CHAR;
// 8-bit character
UTCTL1 |= SSEL0;
// UCLK = ACLK
UBR01 = 0x03;
// 32k/9600 - 3.41
UBR11 = 0x00;
//
UMCTL1 = 0x4A;
// Modulation
UCTL1 &= ~SWRST;
// Initialize USART state
machine
IE2 |= URXIE1;
// Enable USART1 RX interrupt
_BIS_SR(LPM3_bits + GIE);
interrupt
// Enter LPM3 w/
}
#pragma vector=USART1RX_VECTOR
__interrupt void usart1_rx (void)
{
while (!(IFG2 & UTXIFG1)); // USART1 TX buffer
ready?
TXBUF1 = RXBUF1;
// RXBUF1 to TXBUF1
}
- 56 -
IDE
IDE - Create a Project
- 57 -
- 58 -
IDE – Debug 1/2
IDE - Debug 2/2
- 59 -
- 60 -

Microcontroller Programming

Transcript

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